1. Field of the Disclosure
The disclosure relates generally to synchronous digital systems and, more particularly, to synchronous digital systems and methods involving a ramped clock signal.
2. Brief Description of Related Technology
Conventional computing systems record and store data via the absence or presence of a voltage (or charge) in a variety of storage devices, including those commonly referred to as flip-flops. The name “flip-flop” is a reference to the binary nature of the device, as each flip-flop can reside in one of two states. A data “write” operation may initially set and then subsequently reset the state of the flip-flop. When a write operation is desired, input signals are provided to the flip-flop to cause a voltage value representation of the desired state to be applied to a latching circuit in the flip-flop that captures the voltage value. The latching circuit holds the voltage (or charge) to maintain the state of the flip-flop in between successive write operations. In the interim, the state of the flip-flop may be accessed in a “read” operation.
A clock signal is used to establish the timing of each data write to a flip-flop. A typical clock signal has an approximately square waveform. The abrupt step changes of each pulse in a square waveform are desirable for driving the gates of transistors in the flip-flop quickly. A flip-flop is often configured to latch (or capture) the data to be stored on the rising edge of each clock pulse. With a square waveform, the rising edge of the pulse may turn the transistors on or off in a relatively quick manner, enhancing the response time (or operational speed) of the computing system.
FIG. 1 depicts an exemplary, alternative flip-flop indicated generally at 10 and configured to be driven by ramped clock signals, rather than a square waveform, as described in U.S. Pat. No. 6,777,992 (“Low-Power CMOS Flip-Flop”), the entire disclosure of which is hereby incorporated by reference. Like other storage devices, the flip-flop 20 is capable of storing an input value DT at an internal node QT. At the same time, the complement of DT, which is DF, is stored at an internal node QF. The state of node QT is updated in synchrony with a clock signal PCLK. In operation, the flip-flop 10 may receive either a traditional square or ramped clock signal. While the flip-flop may operate with either type of clock waveform, when a ramped clock signal is used, clock signal energy may be recovered from the clock distribution network (including the flip-flop 10) as described in the above-referenced patent.
The flip-flop 10 operates as follows. The data input DT becomes stable at a suitable time before the rising edge of the clock signal PCLK. As the clock signal rises, the cross-coupled PFET devices sense and differentially determine the voltages on the internal nodes XT and XF based on the value of DT. Since the cross-coupled NOR gates form a set/reset latch, a positive pulse on either XT or XF causes the latch to either set or reset, respectively. When DT is not changing, either XT or XF will remain low, with the other node changing in phase with PCLK.
When a ramped clock waveform is used to drive the flip-flop 10, clock energy is recovered from the flip-flop 10 regardless of the state of the latch. As described in the above-referenced patent, charge is transferred to and from the clock signal PCLK in an energy-efficient manner. Briefly stated, the clock distribution network includes an inductor configured to cooperate with the parasitic capacitance of each flip-flop and the clock distribution network to support resonant distribution of the clock signal both to and from the flip-flop 10.
With all of the flip-flops in the network operating, the capacitance of the clock distribution network remains relatively stable. In this way, the inductor provides the appropriate amount of inductance for resonant distribution of the clock signal at the desired frequency. Conversely, if the capacitance were to be modified significantly due to, for instance, interruption of clock signal delivery to one or more flip-flops, then the total capacitance of the network would change, and the clock signal would fall out of resonance. The efficiency of the system would therefore decline, as the distribution of the clock signal would thus recover less energy from the network. The efficiency of the clock energy recovery would also decline unless ideal, zero-resistance switches were used to effectuate the clock signal interruptions.
However, clock signal delivery has often been interrupted to save power. In a typical case, the clock signal is choked at a high level in the distribution network, cutting distribution to entire domains of flip-flops. In other cases, the clock signal has been gated on an individual flip-flop basis. For example, the clock signal may be fed to a NAND gate coupled to the flip-flop. In either case, the clock signal fails to reach the flip-flop, and the capacitance of the distribution network may significantly change.
A pipeline of flip-flops may implement a different power saving technique. In the past, the output of a flip-flop in the pipeline has been fed to a multiplexer to provide the option of disregarding the state of the flip-flop, effectively stalling the pipeline. The pipeline may be stalled for a variety of reasons, but avoiding the unnecessary toggling of downstream flip-flops and combinational logic may also result in power savings.
Unfortunately, conditioning the output of a flip-flop may only be suitable in special configurations of memory cells (e.g., a pipeline). Moreover, even though the clock signal may still be distributed throughout the pipeline, at least some flip-flops in the system (e.g., the flip-flop feeding the multiplexer) are still consuming power.